Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a pipelined discrete-time (DT) SDM. With a DT data converter, an analog input signal (such as signal AIN) is sampled by a sample-and-hold (S/H) circuit (such as S/H circuit 102) at discrete points in time or sampling instants, and the samples are converted to digital. Here, two SDM stages 104-1 and 104-2 are used in a pipeline configuration to perform the conversion for each of the samples. Each of stages 104-1 and 104-2 respectively comprise summing circuits 116-1/118-1 or 116-2/118-2, a delay 120-1 or 120-2, quantizer 122-1 or 122-2, digital low pass filter (LPF) 124-1 or 124-2, and digital-to-analog converter (DAC) 128-1 or 128-2. Additionally, stage 104-1 also includes digital filter 126. Between stages 104-1 and 104-2, there are several other components that enable stages 104-1 and 104-2 to operate as a pipeline; namely, these components are delay 108, summing circuit 110, amplifiers 112 and 114, analog LPF 113, and digital output circuit 106.
In operation, DT SDM 100 converts the analog input signal AIN to digital output signal DOUT. To accomplish this, a sample of the analog input signal AIN is provided to stage 104-1 (by S/H circuit 102), where the sample is converted to digital using conventional sigma-delta modulation. The same sample is provided to delay 108 so as to provide stage 104-1 with sufficient time to perform the data conversion. The difference analog representation of the data conversion (from DAC 128-1) and the sampled analog input signal AIN (from delay 108) or residue is determined by summing circuit 110. This residue is amplified and filtered by amplifiers 112 and 114 and analog LPF 113 and provided to stage 104-2. Stage 104-2 can then convert the residue to digital using conventional sigma-delta modulation. The digital output circuit 106 then generates the digital output signal DOUT based the output from each pipeline 104-1 and 104-2.
This architecture, however, is incompatible with CT sigma-delta modulation. With DT sigma-delta modulation, the input to the stages (i.e., stages 104-1 and 104-2) is constant during conversion because the S/H circuit 102 holds the sampled analog input signal AIN. In contrast, an input to stages of a pipeline would be varying. Looking to DT SDM 100, it specifically employs a delay 108 so that stages 104-1 and 104-2 perform sigma-delta modulation on the same sample. If one were to remove the S/H circuit 102 so as to provide a continuously varying signal (i.e., analog input signal AIN) directly to stage 104-1 and delay 108, DT SDM 100 would not function.
Some other conventional circuits are: U.S. Pat. No. 5,729,230; U.S. Pat. No. 6,788,232; U.S. Pat. No. 7,460,046; U.S. Pat. No. 7,486,214.